The present invention relates to methods for making semiconductor devices, and in particular, semiconductor devices with metal gate electrodes.
When making a complementary metal oxide semiconductor (CMOS) device that includes metal gate electrodes, a replacement gate process may be used to form gate electrodes from different metals. In that process, a first polysilicon layer, bracketed by a pair of spacers, is removed to create a trench between the spacers. The trench is filled with a first metal. A second polysilicon layer is then removed, and replaced with a second metal that differs from the first metal.
Current processes for etching polysilicon layers generate patterned polysilicon layers. A sidewall spacer is used to form graded junction source drain regions. The structure is ultimately filled with an interlayer dielectric. With tight pitch technologies, voids in the interlayer dielectric may be created between gate structures. These voids may render the product unusable.
Accordingly, there is a need for an improved method for making a semiconductor device that includes metal gate electrodes.
Features shown in these Figures are not intended to be drawn to scale.